(www.mri-nyc.com)
Now you can confidently tape out your design ON TIME – Critical end of design “Timing Closure” tool that provides an easy to use, predictable timing closure vehicle for those last 100-200 timing paths that can typically take from 4-8 weeks to resolve. With the “Optimization Cockpit”, the designer can perform fast ECO edits, explore “what if” analysis and achieve timing closure in days instead of weeks.
(www.winterlogic.com)
Improve the Quality of your semiconductor product! High performance software based Fault Simulation of faults not covered by ATPG, using existing functional vectors. The technology includes an “expert” test analysis suite which analyzes the circuit and functional vectors to identify the best test ordering to achieve the highest fault coverage. Fault models supported include, stuck-at, transition and bridge faults.